In the chip production process, EDA tools and IP design do not involve the actual production and manufacturing of chips. However, as the first link in the chip design field, the technological progress of EDA tools/IP cores directly affects the development speed of the chip industry. It is an extremely critical link in the rise of domestic chips, and its importance is comparable to that of lithography machines.

The "2020 Hard Core China Chip" selection event, hosted by Xinshiye, named by Shenzhen Fubao Group, and sponsored by Mouser Electronics with exclusive gifts, aims to commend outstanding domestic semiconductor companies and encourage domestic companies to increase their research and development efforts on IC products and technologies. In this selection, 6 companies were selected for the "Hard Core Chinese Chip - 2020 Domestic EDA/IP Selection". This article takes stock of the EDA tools and IP design products of the selected companies to provide the market with high-quality domestic chip software selection.

Ultra-low power consumption BLE5.2 RF IP

Owned company: Ruicheng Core Micro (ACTT)

This product supports the BLE5.2 protocol and can achieve NF=6dB (-97dBm sensitivity) and 6dBm output power. Power consumption is as low as Rx=6mW, Tx=7mW@0dBm. The formed chip products have been mass-produced by world-class customers, and are well guaranteed in terms of product stability and compatibility.

Price competitiveness: This product is based on CMOS technology and does not require special processes or special devices such as DNW. The entire design uses 1P5M and the area is as low as 0.5 mm². Provide customers with highly competitive advantages in market costs after integrating this product.

Technological innovation: The product adopts an innovative design architecture with built-in Balun and does not require an external resistor matching network. While ensuring performance and low power consumption, it has become the smallest BLE IP in the industry.

Customer service: Based on ACTT’s years of IP service experience and low-power IP technology accumulation, it can provide customers with complete BLE IP solutions. In addition to the complete Designkit of BLE IP, ACTT can provide process migration and product customization of BLE. And cooperate with BLE to provide a package of services such as protocol stack technical support and application software support. ACTT's low-power analog IP, eNVM IP and interface IP, together with BLE IP, form a platform-based IP solution that supports various CPU architectures. Customers can select and tailor these IPs to quickly form the specifications they need. Based on ACTT's system integration experience, it can greatly reduce design risks, save development costs, and shorten time to market.

Market sales: BLE IP has been continuously supplied to customers for shipments in 55nm for many years, supporting many major customers at home and abroad. The BLE IP designed based on 40nm has been adopted by customers as soon as it is launched. At the same time, 28nm has also cooperated with customers and started design.

Gowin Yunyuan? Software logic synthesis tool GowinSynthesis1.9.6

Owned company: Gowin Semiconductor

Gowin Yunyuan? Software logic synthesis tool GowinSynthesis1.9.6 supports Verilog/SystemVerilog, VHDL mixed design input, supports ultra-large-scale design, and provides industry-leading FPGA physical synthesis solutions, improving the quality of comprehensive results by 10% and overall efficiency by 20%;

Price competitiveness: Currently, when purchasing Gowin FPGA chips, a license for high-performance comprehensive tools is provided free of charge;

Technological innovation: Completely domestically produced EDA tools, whose performance exceeds that of similar products from internationally renowned brands, providing excellent HDL comprehensive solutions for complex programmable logic design;

Customer service: Combined with Gowin Yunyuan design software, easy to use and debug, Gowin provides original technical support to ensure the quality of customer service;

Market sales: Since GowinSynthesis was released with Gowin Yunyuan software 1.9.0 (February 2019), it has been fully recognized by customers in terms of compilation quality and user experience. GowinSynthesis has become the default comprehensive tool for Gowin’s full range of FPGA chip development.       

Huaxia Core 64-bit multi-core processor IP GPTX2 CPU

Owned company: Huaxia Chip

GPTX2 CPU is Huaxia Core's multi-core processor IP with completely independent intellectual property rights, supporting processor clusters from a single core to four GPTX2 CPU cores. The GPTX2 CPU core is a 64-bit superscalar processor based on RISC architecture. It has a highly optimized 3-issue pipeline and supports hybrid branch prediction and out-of-order guessing execution. The non-uniform register file enables the superscalar pipeline to run at higher clock speeds. With the assistance of compiler technology, it can accelerate many functional components of the processor.

The GPTX2 architecture is based on advanced process design and provides industry-leading performance and energy efficiency ratio. It is suitable for high-performance parallel computing applications in embedded fields such as assisted driving systems (ADAS), robots, AR/VR, intelligent monitoring, and edge computing.

AGP2122 NB-IOT/GNSS Transceiver RFIP

Owned company: Xingjixingyuan

AGP2122 is the first domestically successfully commercially authorized 5G NB-IOT/GNSS dual-mode Transceiver RFIP independently developed by Xingjiexingyuan. It has the following innovations:

1. Supports NB-IOT/GNSS dual mode, compatible with 3GPP R15 FDD standard, supports R15 standard FDD frequency band, and supports GNSS navigation frequencies (L1, B1, E1);

2. Adopt low-IF receiver and polar transmitter structure (Polar Transmitter) to achieve ultra-low power consumption design;

3. The low-pass filter and VGA of the receiving channel and transmitting channel adopt time-division multiplexing to save chip area, greatly simplify the circuit design and reduce the cost;

4. Both transceiver and transceiver channels support IQ amplitude and phase balance calibration to improve receiving image suppression and reduce transmitting EVM.

5. Integrate a high linearity power amplifier to reduce system application costs.

6. Integrate DCXO to reduce system application costs.

The receiving power consumption of AGP2122 is only 60% of that of similar RFIPs, and its area is only 70% of that of similar RFIPs. It is currently the only 5G NB-IOT/GNSS dual-mode Transceiver RFIP in China that integrates a 23dBm CMOS PA. It has been successfully authorized to well-known domestic customers and the European market, with more than one million units shipped in mass production.

Xinlai 600 series RISC-V processor

Owned company: Xinlai Technology

Xinlai 600 series RISC-V processors are completely independently developed and designed by Xinlai Technology's local team. Like previous products, they are built with robust enterprise-level Verilog code, which can be fully traced and reset to ensure the reliability and safety of users. Aiming at real-time control of AIoT edge computing and high-performance embedded applications that require complete operating system support, it is suitable for application scenarios such as artificial intelligence, storage, smart TVs, and broadband gateways.

performance:

Support RV64IMACFDP

Supports user mode and PMP

Support hardware multiplication and division

Configurable instruction cache (I-Cache) of any size, with ECC function

Configurable data cache (D-Cache) of any size, with ECC function

Configurable ILM and DLM of any size to improve performance and real-time performance

Configurable user-defined command interface

Configurable AHB-Lite private external design interface

Configurable slave interface

Configurable fast I/O interface

Configurable timing boost

Configurable MMU

Configurable SIMD DSP unit

Configurable hardware single precision floating point unit

Configurable supervision mode and Trusted Execution Environment TEE

Dhrystione standard running score is 1.7DMIPS/MHz

CoreMark running score is 3.03CoreMark/MHz

Soft ecological support:

The 600 series processors fully support Nuclei Software Platform NSP (Nuclei Software Platform). NMSIS is a vendor-independent hardware abstraction layer defined for Nuclei Technology RISC-V processors. It defines a common tool interface and provides continuous processor device support, as well as a simple software access interface API for processors and peripherals. Adopting the NMSIS framework can greatly improve the reusability of application software, shorten the learning time of RISC-V microprocessor developers, and shorten the time to market of new products based on Core IP.

Nuclei SDK is a software development kit specially developed for SoC based on Xilai Technology's Nuclei processor core. Nuclei SDK is developed based on NMSIS and provides all functions on NMSIS, including NMSIS-Core, NMSIS-NN, and NMSIS-DSP. Nuclei SDK provides bare-metal and real-time operating system (FreeRTOS, μC/OS-II) development environments.

Toolchain support:

While Xinlai Technology provides complete Nuclei Studio and Hummingbird debuggers, it currently fully supports SEGGER's Embedded Studio and J-Link tools; Lauterbach's Development Tool and TRACE32® debugger; and IAR's development environment and debugging tools.

FPGA Evaluation Kit:

Xinlai Technology has customized a dedicated hardware development board and dedicated JTAG debugger based on Xilinx XC7A200T FPGA so that 600 series users can quickly transplant processor core products and supporting MCU prototype SoCs.

ANX2403 ultra-low power full HD embedded DisplayPort?

1.4(eDP) Timing Controller (TCON)

Owned company: Analogix Silicon Valley

The ANX2403 is the product of Analogix's comprehensive capabilities in low-power processes, in-cell touch technology and high dynamic range (HDR) technology. Its power consumption is by far the lowest in the industry. It not only improves image performance, but also achieves a slim frame design, which not only reduces the cost of display panel manufacturers, but also makes its panels thinner and lighter.

This TCON is the industry's lowest power consumption full HD eDP timing controller, using 28nm process technology to reduce full HD 60Hz power consumption to 60mW. Its power consumption is 35% lower than that of 40nm process technology, and more than 50% lower than that of 55nm process technology, making it the timing controller with the lowest power consumption in the industry. In addition, ANX2403 also supports Intel's low refresh rate (LRR) and PSR2, which can further reduce power consumption. The implementation of low power consumption has many different dimensions. The improvement of process technology is the most important impact.

In addition, we have also brought further reduction in power consumption to the system through PSR. PSR is a self-refresh technology. With the support of this technology, there will be a buffer inside TCON to maintain image display, without the need to receive video data from the front end. If it is a still image, the GPU can enter a low-power state and the eDP main link is closed; even if it is a dynamic image, there may still be multiple frames with unchanged content, so power consumption can also be saved. The later PSR2 further implemented the transmission of only the modified picture area, that is, selective transmission.

In addition to the better power consumption performance brought by the previously mentioned process and PSR, "there is another point, the transmission speed of DisplayPort is relatively high. ANX2403 uses eDP 1.4 - in the implementation of eDP, Silicon Valley Analog Devices itself has some unique secrets to achieve low power consumption, so whether it is 55nm or 28nm, we can maintain lower power consumption than competitors.

eLinkSeas 06 eFPGA IP core

Owned company: Zhongke Yihaiwei

eLinkSeas adopts a cost-effective LUT4 logic unit structure, which can support a typical integration range of 640 to 92,000 logic units. It integrates a programmable block memory BRAM unit based on 4Kbit size, which can realize various types of RAM, ROM, and Shift with different bit width modes and different clock modes. Register and FIFO integrate digital signal processing DSP resources, which can support 9×9, 18×18, 36×36 multiplication, addition, subtraction, accumulation and sum operations. It can provide flexible pin density according to needs. The typical pin density is 240 pairs of input and output Pin@1000LUTs, the typical quiescent current is as low as 0.3mA@1000LUTs, and the clock frequency can reach more than 500MHz. Compared with the most advanced products of the same node from leading foreign companies, it is far ahead in aspects such as pin density, power consumption, customized design services, and integration flexibility.

Price competitiveness: Compared with the corresponding IP core products of foreign leading eFPGA providers, the price is less than 1/4.

Technological innovation: The first eFPGA IP core based on domestic advanced technology and the first independent "array scale/computing resource user-defined" compilation technology (has applied for multiple Chinese invention patents and software copyrights). It can quickly customize and generate embedded FPGA IP cores with different resources, layout physical sizes and shapes according to different user application needs, filling the gap in my country's independent process eFPGA and setting a benchmark for domestically produced eFPGA IP core products.

Customer service: We have mature eFPGA software and hardware compilation technology. Under certain specifications, we can provide SoC users with the required GDS and related files within 1 to 2 months, which is significantly shorter than the 3 to 6 month design cycle of foreign benchmark products. And relying on existing technical advantages, we can provide users with customized programmable circuit modules and "layout-transistor-circuit-system" level complete solutions for different application needs, such as reinforced IP cores for high reliability requirements, convolution operation acceleration cores for deep learning, matrix operation acceleration modules for high-throughput data signal processing, etc. It supports customers' integrated development throughout the entire process, and is rated as "the most standard eFPGA IP provider in China" by customers.

Market sales: eLinkSeas eFPGA IP core has been authorized to many domestic SoC user units and provides them with integrated complete solutions. Many of the SoC chips will be tape-out by the end of the year or in the middle of next year. The annual sales of the IP core are conservatively estimated to reach more than 10 million.

Note: This article is reproduced from the Internet and supports the protection of intellectual property rights. Please indicate the original source and author when reprinting. If there is any infringement, please contact us to delete it.

Company phone number: +86-0755-83044319
Fax/FAX: +86-0755-83975897
Email: 1615456225@qq.com
QQ: 3518641314 Manager Li

QQ: 332496225 Manager Qiu

Address: Room 809, Building C, Zhantao Technology Building, No. 1079 Minzhi Avenue, Longhua New District, Shenzhen