There are historical reasons why a technology can become well-known from a relatively narrow professional field, and it is also inseparable from the promotion of well-known companies. It is Apple that brought SiP to the public, and it is because of TSMC that advanced packaging can attract widespread public attention. Apple said that its iWatch uses SiP technology, and SiP has been widely known since then; TSMC said that in addition to advanced technology, it also needs to engage in advanced packaging. Therefore, advanced packaging has been mentioned by the industry as being as important as advanced technology. In recent years, advanced packaging technologies have continued to emerge, and new terms have emerged one after another, which is somewhat confusing. Currently, there are at least dozens of names related to advanced packaging that can be listed. For example: WLP (Wafer Level Package), FIWLP (Fan-in Wafer Level Package), FOWLP (Fan-Out Wafer Level Package), eWLB (embedded Wafer Level BallGrid Array), CSP (Chip Scale Package), WLCSP (Wafer Level Chip Scale Package), CoW (Chip on Wafer), WoW (Wafer on Wafer), FOPLP (Fan-Out Panel Level Package), InFO(Integrated Fan-Out), CoWoS(Chip-on-Wafer-on-Substrate), HBM(High-Bandwidth Memory), HMC(Hybrid MemoryCube), Wide-IO(Wide Input Output), EMIB(Embedded Multi-Die Interconect Bridge), Foveros, Co-EMIB, ODI(Omni-Directional Interconnect), 3D IC, SoIC, X-Cube...etc...these are advanced packaging technologies. How to distinguish and understand these dazzling advanced packaging technologies? This is what this article wants to tell readers. First, for ease of differentiation, we divide advanced packaging into two categories:① Advanced packaging technology based on XY plane extension, mainly through RDL for signal extension and interconnection;② Advanced packaging technology based on Z-axis extension, mainly through TSV for signal extension and interconnection.  
   Based on XY plane extension Advanced packaging technology
 

The XY plane here refers to the wafer or the XY plane of the chip. The distinctive feature of this type of package is that there is no TSV through silicon hole. The signal extension means or technology is mainly implemented through the RDL layer. There is usually no substrate. The RDL wiring is attached to the silicon body of the chip or on additional molding. Because the final packaged product does not have a substrate, such packages are relatively thin and are currently widely used in smartphones.

1．FOWLP

FOWLP (Fan-out Wafer Level Package) is a type of WLP (Wafer Level Package), so we need to understand WLP wafer level packaging first.

Before the emergence of WLP technology, the traditional packaging process steps were mainly carried out after cutting and slicing the die. The wafer was first cut and diced, and then packaged into various forms.

WLP came out around 2000. There are two types: Fan-in (fan-in) and Fan-out (fan-out). WLP wafer-level packaging is different from traditional packaging. In the packaging process, most of the process is to operate the wafer, that is, overall packaging (Packaging) is performed on the wafer, and after the packaging is completed, it is cut into slices. Because it is cut into pieces after packaging is completed, the size of the packaged chip is almost the same as that of the bare chip, so it is also called CSP (Chip Scale Package) or WLCSP (Wafer Level Chip Scale Packaging). This type of packaging conforms to the market trend of light, small, short, and thin consumer electronic products. The parasitic capacitance and inductance are relatively small, and it has the advantages of low cost and good heat dissipation.

At first, WLP mostly adopted the Fan-in type, which can be called Fan-in WLP or FIWLP. It is mainly used in chips with smaller area and fewer pins.

As IC technology improves, the chip area shrinks, and the chip area cannot accommodate enough pins. Therefore, the Fan-Out WLP packaging form, also known as FOWLP, is derived, which makes full use of RDL for connections outside the chip area to obtain more pins.

In FOWLP, since RDL and Bump are to be led out to the periphery of the bare chip, the bare chip wafer needs to be diced and segmented first, and then the independent bare chips are reconfigured into the wafer process. Based on this, through batch processing and metallized wiring interconnection, the final package is formed. The FOWLP encapsulation process is shown in the figure below.

FOWLP is supported by many companies, and different companies have different naming methods. The figure below shows the FOWLP provided by major companies.

Whether using Fan-in or Fan-out, the connection between WLP wafer-level packaging and PCB is in the form of flip chip. The active side of the chip faces down towards the printed circuit board, which can achieve the shortest electrical path, which also ensures higher speed and less parasitic effects. On the other hand, due to the use of batch packaging, the entire wafer can be packaged at once, and cost reduction is another driving force for wafer-level packaging.  2．INFOInFO (Integrated Fan-out) is an advanced FOWLP packaging technology developed by TSMC in 2017. It is an integration of the FOWLP process and can be understood as the integration of multiple chip Fan-Out processes, while FOWLP focuses on the Fan-Out packaging process itself. InFO gives space for multiple chip integration and can be applied to the packaging of radio frequency and wireless chips, processor and baseband chip packaging, graphics processors and network chips. The figure below is a comparison diagram of FIWLP, FOWLP and InFO.

Apple's iPhone processors have been produced by Samsung in the early years, but TSMC has taken orders for two generations of iPhone processors, starting with the Apple A11. One of the keys is TSMC's new packaging technology InFO, which allows chips to be directly interconnected, reducing thickness and freeing up valuable space for batteries or other parts.

Apple started using InFO packaging with the iPhone 7 and will continue to use it. iPhone 8, iPhone X, and other mobile phone brands in the future will also begin to use this technology. The joining of Apple and TSMC has changed the application status of FOWLP technology and will enable the market to gradually accept and widely apply FOWLP (InFO) packaging technology.  3．FOPLPFOPLP (Fan-out Panel Level Package) panel-level packaging draws on the ideas and technology of FOWLP, but uses a larger panel, so it can mass-produce packaged products several times that of 300 mm silicon wafer chips. FOPLP technology is an extension of FOWLP technology. It performs the Fan-Out process on a larger square carrier board, so it is called FOPLP packaging technology. The Panel carrier board can be a PCB carrier board or a glass carrier board for LCD panels. Currently, FOPLP uses a 24-18-inch (610-457mm) PCB carrier board, whose area is about 4 times that of a 300 mm silicon wafer. Therefore, it can be simply regarded as a single process that can mass-produce advanced packaging products that are 4 times the size of a 300 mm silicon wafer. Like the FOWLP process, FOPLP technology can integrate the front-end and back-end processes of packaging. It can be regarded as a one-time packaging process, so it can significantly reduce production and material costs. The picture below shows the comparison between FOWLP and FOPLP.

FOPLP uses PCB production technology to produce RDL. Its line width and line spacing are currently greater than 10um. It uses SMT equipment to mount chips and passive components. Since its panel area is much larger than the wafer area, more products can be packaged at one time. Compared with FOWLP, FOPLP has a greater cost advantage. Currently, major packaging companies around the world, including Samsung Electronics and ASE, are actively investing in FOPLP process technology.  4．EMIBEMIB (Embedded Multi-Die Interconnect Bridge) embedded multi-chip interconnect bridge advanced packaging technology was proposed and actively applied by Intel. Different from the three advanced packages described previously, EMIB is a substrate-based package. Because EMIB does not have TSV, it is also classified as an advanced packaging technology based on XY plane extension. The EMIB concept is similar to 2.5D packaging based on silicon interposers, which is local high-density interconnection through silicon wafers. Compared with traditional 2.5-inch packaging, EMIB technology has the advantages of normal packaging yield, no need for additional processes, and simple design because there is no TSV. Traditional SoC chips, CPU, GPU, memory controller and IO controller can only be manufactured using one process. Using EMIB technology, CPU and GPU have high process requirements and can use 10nm process. IO unit and communication unit can use 14nm process, and the memory part can use 22nm process. Using EMIB advanced packaging technology, three different processes can be integrated into one processor. The picture below is a schematic diagram of EMIB.    

Compared with silicon interposers, EMIB silicon wafers are smaller, more flexible, and more economical. EMIB packaging technology can package CPU, IO, GPU and even FPGA, AI and other chips together as needed. It can package chips of 10nm, 14nm, 22nm and other different processes together into a single chip to meet the needs of flexible business.

Through EMIB, the KBL-G platform integrates Intel Core processors and AMD Radeon RX Vega M GPUs. It combines the powerful computing capabilities of Intel processors with the excellent graphics capabilities of AMD GPUs, and has an excellent cooling experience. This chip made history and brought product experience to a new level.

   Based on Z-axis extension Advanced packaging technology  

Advanced packaging technology based on Z-axis extension mainly uses TSV for signal extension and interconnection. TSV can be divided into 2.5D TSV and 3D TSV. Through TSV technology, multiple chips can be vertically stacked and interconnected.

In 3D TSV technology, chips are very close to each other, so there will be less delay. In addition, the shortened interconnect length can reduce related parasitic effects, allowing the device to run at higher frequencies, which translates into performance improvements and greater cost reductions. TSV technology is a key technology for three-dimensional packaging. Research institutions including semiconductor integrated manufacturers, integrated circuit manufacturing foundries, packaging foundries, emerging technology developers, universities and research institutes, and technology alliances have conducted various research and development on TSV processes. In addition, readers need to note that although advanced packaging technology based on Z-axis extension mainly performs signal extension and interconnection through TSV, RDL is also indispensable. For example, if the TSVs of the upper and lower chips cannot be aligned, local interconnection through RDL is required.    5．CoWoS
CoWoS (Chip-on-Wafer-on-Substrate) is a 2.5D packaging technology launched by TSMC. CoWoS packages the chip onto a silicon adapter board (interposer), uses high-density wiring on the silicon adapter board for interconnection, and then installs it on the packaging substrate, as shown in the figure below.

CoWoS and the previously mentioned InFO are both from TSMC. CoWoS has a silicon interposer, but InFO does not. CoWoS is aimed at the high-end market, with a relatively large number of connections and package size. InFO is aimed at the cost-effective market, with a smaller package size and a smaller number of connections.

TSMC began mass production of CoWoS in 2012. Through this technology, multiple chips are packaged together and interconnected through high-density Silicon Interposer, achieving the effects of small package size, high performance, low power consumption, and fewer pins.

CoWoS technology is widely used. Nvidia's GP100 and the Google chip TPU2.0 behind AlphaGo that defeated Ke Jie all use CoWoS technology. Artificial intelligence AI also has CoWoS contributions. Currently, CoWoS has received support from high-end chip manufacturers such as NVIDIA, AMD, Google, XilinX, and Huawei HiSilicon.

6．HBMHBM (High-Bandwidth Memory) high-bandwidth memory, mainly targeted at the high-end graphics card market. HBM uses 3D TSV and 2.5D TSV technology to stack multiple memory chips together through 3D TSV, and uses 2.5D TSV technology to interconnect stacked memory chips and GPUs on the carrier board. The figure below shows a schematic diagram of HBM technology.

HBM currently has three versions, namely HBM, HBM2 and HBM2E, with bandwidths of 128 GBps/Stack, 256 GBps/Stack and 307 GBps/Stack respectively. The latest HBM3 is still under development. The HBM standard is promoted by AMD, NVIDIA and Hynix. AMD was the first to use the HBM standard in its flagship graphics card, with a memory bandwidth of up to 512 GBps. NVIDIA followed suit and used the HBM standard to achieve a memory bandwidth of 1TBps. Compared with DDR5, HBM performance is improved by more than 3 times, but power consumption is reduced by 50%.  7．HMCHMC (Hybrid Memory Cube) hybrid storage cube, its standard is mainly promoted by Micron, and its target market is the high-end server market, especially for multi-processor architecture. HMC uses stacked DRAM chips to achieve greater memory bandwidth. In addition, HMC integrates the memory controller into the DRAM stack package through 3D TSV integration technology. The figure below shows a schematic diagram of HMC technology.

Comparing HBM and HMC, we can see that they are very similar. Both DRAM chips are stacked and interconnected through 3D TSV, and there are logic control chips underneath. The difference between the two is: HBM is interconnected through Interposer and GPU, while HMC is installed directly on Substrate, lacking Interposer and 2.5D TSV in the middle. In the HMC stack, the diameter of 3D TSV is about 5~6um, and the number exceeds 2000+. DRAM chips are usually thinned to 50um, and the chips are connected through 20um MicroBump. In the past, memory controllers were built into the processor, so in high-end servers, when a large number of memory modules need to be used, the design of the memory controller is very complex. Now that the memory controller is integrated into the memory module, the design of the memory controller is greatly simplified. In addition, HMC uses a high-speed serial interface (SerDes) to implement a high-speed interface, which is suitable for situations where the processor and memory are far apart.  8．Wide-IOWide-IO (Wide Input Output) broadband input and output technology is mainly promoted by Samsung. It has now reached the second generation. It can achieve a memory interface width of up to 512bit. The memory interface operating frequency can reach up to 1GHz. The total memory bandwidth can reach 68GBps, which is twice the bandwidth of the DDR4 interface (34GBps). Wide-IO is implemented by stacking the Memory chip on the Logic chip. The Memory chip is connected to the Logic chip and substrate through 3D TSV, as shown in the figure below.

Wide-IO has the vertical stacking packaging advantages of the TSV architecture, which helps create mobile memories with speed, capacity and power characteristics to meet the needs of mobile devices such as smartphones, tablets, and handheld game consoles. Its main target market is mobile devices that require low power consumption.  9．FoverosIn addition to the EMIB advanced packaging introduced earlier, Intel also launched Foveros active onboard technology. In Intel's technology introduction, Foveros is called 3D Face to Face Chip Stack for heterogeneous integration, a three-dimensional face-to-face heterogeneous integrated chip stack. The difference between EMIB and Foveros is that the former is a 2D packaging technology, while the latter is a 3D stacking packaging technology. Compared with the 2D EMIB packaging method, Foveros is more suitable for small-size products or products with higher memory bandwidth requirements. In fact, there is not much difference between EMIB and Foveros in terms of chip performance and functions. They both integrate chips of different specifications and functions to play different roles. However, in terms of size and power consumption, the advantages of Foveros 3D stacking are revealed. The power of each bit of data transmitted by Foveros is very low. Foveros technology has to deal with the reduction of Bump spacing, the increase of density and the chip stacking technology. The figure below shows the schematic diagram of Foveros 3D packaging technology.

LakeField, the first Foveros 3D stacked motherboard chip, integrates a 10nm Ice Lake processor and a 22nm core. It has complete PC functions but is only the size of a few cents. Although Foveros is a more advanced 3D packaging technology, it is not a substitute for EMIB. Intel will combine the two in subsequent manufacturing.  10．Co-EMIB（Foveros + EMIB）Co-EMIB is a combination of EMIB and Foveros. EMIB is mainly responsible for horizontal connections, allowing chips with different cores to be spliced ​​together like a puzzle. Foveros is stacked vertically, just like building a high-rise building. Each floor can have a completely different design. For example, the first floor is a gym, the second floor is an office building, and the third floor is an apartment. The packaging technology that combines EMIB and Foveros is called Co-EMIB, which is a more flexible chip manufacturing method that allows chips to continue to be spliced ​​horizontally while being stacked. Therefore, this technology can splice multiple 3D Foveros chips together through EMIB to create a larger chip system. The picture below is a schematic diagram of Co-EMIB technology.

Co-EMIB packaging technology can provide performance comparable to that of a single chip. The key to achieving this technology is ODI (Omni-Directional Interconnect) omnidirectional interconnection technology. ODI has two different types. In addition to elevator-type connections that connect different layers, there are also overpasses that connect different three-dimensional structures, as well as mezzanines between layers, allowing different chip combinations to have extremely high flexibility. ODI packaging technology allows chips to achieve both horizontal and vertical interconnections.

Co-EMIB uses a new 3D + 2D packaging method to change chip design thinking from the past flat puzzle to stacking blocks. Therefore, in addition to revolutionary new computing architectures such as quantum computing, CO-EMIB can be said to be the best practice in maintaining and continuing the existing computing architecture and ecosystem.

11．SoIC

SoIC, also known as TSMC-SoIC, is a new technology proposed by TSMC - System-on-Integrated-Chips. It is expected that TSMC's SoIC technology will be mass-produced in 2021. What exactly is SoIC? The so-called SoIC is an innovative multi-chip stack technology that can integrate processes at the wafer level below 10 nanometers. The most distinctive feature of this technology is the no-bump bonding structure, which results in higher integration density and better operating performance. SoIC includes two technical forms: CoW (Chip-on-wafer) and WoW (Wafer-on-wafer). From the description of TSMC, SoIC is a direct bonding (Bonding) technology of WoW wafer to wafer or CoW chip to wafer, which belongs to Front-End 3D technology (FE 3D), while the aforementioned InFO and CoWoS belong to Back-End 3D technology (BE 3D). TSMC and Siemens EDA (Mentor) cooperate on SoIC technology and launch related design and verification tools. The figure below is a comparison of 3D IC and SoIC integration.

Specifically, the manufacturing processes of SoIC and 3D IC are somewhat similar. The key to SoIC is to achieve a joint structure without bumps, and its TSV density is also higher than that of traditional 3D IC. The interconnection between multi-layer chips is directly realized through extremely small TSV. As shown in the figure above, it is a comparison of TSV density and Bump size in 3D IC and SoIC. It can be seen that the TSV density of SoIC is much higher than that of 3D IC. At the same time, the interconnection between its chips also uses no-bump direct bonding technology. The chip spacing is smaller and the integration density is higher. Therefore, its products also have higher functional density than traditional 3D IC.  12．X-CubeX-Cube (eXtended-Cube) is a 3D integration technology announced by Samsung that can accommodate more memory in a smaller space and shorten the signal distance between units. X-Cube is used in processes that require high performance and bandwidth, such as 5G, artificial intelligence, and wearable or mobile devices and applications that require high computing power. X-Cube uses TSV technology to stack SRAM on top of logic cells, which can accommodate more memory in a smaller space. As can be seen from the X-Cube technology demonstration, unlike the previous 2D parallel packaging of multiple chips, X-Cube? 3D packaging allows multiple chips to be stacked and packaged, making the finished chip structure more compact. TSV technology is used to connect the chips, which reduces power consumption while increasing the transmission rate. This technology will be used in the most cutting-edge fields such as 5G, AI, AR, HPC, mobile chips, and VR.

X-Cube technology significantly shortens the signal transmission distance between chips, increases data transmission speed, reduces power consumption, and can also customize memory bandwidth and density according to customer needs. At present, X-Cube technology can already support 7nm and 5nm processes. Samsung will continue to cooperate with global semiconductor companies to deploy this technology in a new generation of high-performance chips.  
    Summarize  Advanced packaging technologyIn this article, we describe 12 of today’s most mainstream advanced packaging technologies. The following table is a horizontal comparison of these mainstream advanced packaging technologies.

From the comparison, we can see that the emergence and rapid development of advanced packaging mainly occurred in the past 10 years. Its integration technology mainly includes 2D, 2.5D, 3D, 3D+2D, 3D+2.5D. The functional density also includes low, medium, high and extremely high. The application fields include It covers 5G, AI, wearable devices, mobile devices, high-performance servers, high-performance computing, high-performance graphics cards and other fields. The main application manufacturers include well-known chip manufacturers such as TSMC, Intel, and SAMSUNG, which also reflects the trend of integration of advanced packaging and chip manufacturing.

Finally, let us summarize: the purpose of advanced packaging is:

Improve functional density, shorten interconnection length, improve system performance, and reduce overall power consumption.

Advanced packaging also puts forward new requirements for EDA tools. EDA tools need to support FIWLP, FOWLP, 2.5DTSV and 3D TSV design, as well as multi-substrate design. Because the silicon interposer and packaging substrate (Substrate) are often integrated together in a product, major EDA companies have launched new tools to support the design and verification of advanced packaging, including Synopsys, Cadence, Siemens EDA (Mentor) is actively involved.

The figure below shows a screenshot of the advanced packaging design of Siemens EDA XPD tool. The design includes 3D TSV and 2.5D TSV design, Interposer, Substrate, FlipChip, Microbump, BGA and other elements, which are detailed and accurately reflected in the EDA tool. For detailed design methods of advanced packaging, please refer to the new book "Microsystems Based on SiP Technology" to be published in the near future.

Typical advanced packaging design (Siemens EDA XPD design screenshot)

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